`timescale 1ns/1ps
module tb1 ();
	bit clk ;
	bit rst_n ;
	logic div_freq_out ;

	initial begin
		clk = 0 ;
		rst_n = 0 ;
		#10 ;
		rst_n = 1 ;
		$display("\t---reset over ! start !---\t");
		#100 ;
		$finish;
	end
	always #2 clk = ~clk ;

	

	initial begin
		$dumpfile("wave.vcd" );
		$dumpvars(0, tb1 ) ;

	end
	always @(posedge  clk or negedge clk )begin
		if(rst_n == 1 && div_freq_out == 1 ) begin
			$display("*");
		end else begin
			$display("_");
		end
	end
	freq_div5 inst_freq_div5 (.clk(clk), .rst_n(rst_n), .div_freq_out(div_freq_out));
endmodule : tb1